Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to a combination of one or more data bit values that may be stored in a given cell. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Arrays of analog memory cells are typically erased before they are used for storing data. A memory cell array is usually partitioned into cell groups, referred to as erasure blocks, which are erased simultaneously. In many memory devices, one of the programming levels is defined as an erased level, and the cells are erased by applying erasure pulses or voltages. Often, the erased level corresponds to a negative threshold voltage, and the cells are erased by applying negative erasure pulses. Various techniques are known in the art for erasing analog memory cells and for verifying that the cells are erased properly.
For example, U.S. Patent Application Publication 2004/0114437, whose disclosure is incorporated herein by reference, describes a method of erasing a nonvolatile memory so as to compact the distribution of erased cell threshold voltages within a restricted range around a target erased threshold voltage. Erase pulses are applied to the cells until a determination is made that adequate erasure has been realized. Once erasure has been verified, the distribution of erased threshold voltages is compacted by sustaining, for a predetermined length of time, the simultaneous application of a gate voltage that is equal to the target erased threshold voltage and a highly positive drain voltage.
U.S. Pat. No. 5,237,535, whose disclosure is incorporated herein by reference, describes a method of repairing over-erased cells in a Flash memory array, which includes a column having a first cell and a second cell. Repair begins by determining whether the first cell is over-erased and applying a programming pulse if so. Next, the second cell is examined to determine whether it is over-erased. A programming pulse is applied to the second cell if it is over-erased. Afterward, if either of the cells was over-erased, the repair pulse voltage level is incremented. These steps are repeated until none of the cells in the column is identified as over-erased.